More and more applications have been found for nonvolatile memories such as flash memories. For example, it is popular to use flash memories in mobile phones, digital cameras, personal digital assistants and portable drives. Currently, memory card is one of the most popular products of flash memories, in which a controller chip is used to control the receiving of data from a host such as a card reader, and the writing of the data into the flash memory. However, the memory card is designed with more and more memory capacity, and to increase the memory capacity of a memory card, there are usually two solutions, one is to increase the memory capacity of single flash memory chip, and the other is to increase the number of flash memory chips in a memory card. For the latter case, the power consumption during the operation of the flash memories in a memory card becomes a thorny problem.
FIG. 1 shows the operational current when a flash memory chip operates upon an erase instruction, and FIG. 2 shows the total operational current when two flash memory chips are simultaneously erased. Typically, a flash memory chip may require a peak current more than 100 mA when it is erased. For example, in a memory card composed of a controller chip with the serial no. SK6626AAPC and flash memory chips with the serial no. TC58NVG3D1D, single flash memory chip requires an extra current between 125 mA and 133 mA when it is erased, as shown in FIG. 1. The extra current is referred to the difference between the maximum and the minimum of an operational current. As shown in FIG. 2, when two flash memory chips are simultaneously erased in a word mode, the extra current becomes about 230 mA to 239 mA. Briefly, the peak current caused by the simultaneous operations of several flash memory chips in a conventional flash memory system is proportional to the number of the flash memory chips. A great peak current will bring the power supply into unstable condition and thereby degrade the stability and reliability of the operation of the host, the controller chip and the flash memory chip.
Conventionally, the solution for this peak current issue is directed to the improvement of the hardware design of the memory system itself, so as to source the power for different components at different time points, which are conventionally provided power at a same time. For example, U.S. Pat. Nos. 7,085,189, 7,224,617 and 7,200,062 are such arts. In U.S. Pat. No. 7,085,189, flash memory ships are divided into four banks for data storage, among which three are added with delay circuit such that the four memory banks will be erased at different time points upon an erase instruction, so as to reduce the peak current when the four memory banks are to be erased. U.S. Pat. No. 7,224,617 provides a high speed operation mode and a low current consumption mode for a flash memory system, and in the high speed operation mode, if the peak current causes the flash memory system and the host it is connected unstable, the system will switch to the low current consumption mode. U.S. Pat. No. 7,200,062 sets different time delays for different DRAM chips when the system is to refresh the DRAM chips, so as to decentralize the peak current produced by the refresh operation.
However, prior arts all focus on improving the hardware design of the memory system to decentralize the intensity and the occurrence time of the peak current, which needs to change the hardware design and is less flexibility. Therefore, an alternative approach which does not require to change the hardware design of a nonvolatile memory system to decentralize the peak current thereof is desired.